Z80 Lab

A browser-only Z80 assembler and emulator. Edit assembly, run it, step one instruction, and watch registers, flags, T-states, memory, bytes, and port-1 console output change. No backend runs user code.

Port 1 is wired to the console: OUT (1),A prints a character. The Run loop stops when HALT is reached and labels the CPU halted; a real Z80 would keep executing NOPs until an interrupt.
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SOURCE

STATE

T-states: 0 · 0.000 ms at 3.5 MHz

CONSOLE


    
MEMORY AROUND PC

    
INSTRUCTION TIMING / BYTES

    
SELF-TEST

    
Implemented: labels, org, db/defb, dw/defw, ds/defs, equ, expressions, core documented opcodes, IX/IY displacement, CB shifts/bit ops, ED block ops, IN/OUT. Out of scope: undocumented opcodes, IXH/IXL/IYH/IYL halves, interrupt modes/servicing, and R-register emulation. Any unsupported opcode raises a visible error naming the byte and address. Timing uses the emulator's documented Zilog uncontended M1-cycle table; after Run or Step, the listing shows each executed instruction's T-states and running total.

  




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